1. Field
Embodiments of the present invention relate to a semiconductor device manufacturing method.
2. Description of the Related Art
Generally, as power semiconductor elements used in a power conversion device or the like, there are elements that carry out a switching operation, such as a power metal-oxide semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT), a freewheeling diode (FWD) used in combination with these elements, and the like.
For example, an IGBT is a power semiconductor element having the high speed switching characteristics and voltage drive characteristics of a MOSFET and the low on-state voltage characteristics of a bipolar transistor. Hereafter, a description will be given of structures of an IGBT. Structures of an IGBT include a punch through (PT) type, a non-punch through (NPT) type, a field stop (FS) type, and the like.
A PT type IGBT is fabricated (manufactured) using an epitaxial substrate wherein an n-type buffer layer and an n− type active layer are epitaxially grown on a surface of a p+ type semiconductor substrate. For example, in the case of an element in a 600V breakdown voltage class, an active layer thickness of in the region of 100 μm is sufficient, and the total thickness of the epitaxial substrate including the p+ type semiconductor substrate is in the region of 200 to 300 μm. Also, as a PT type IGBT is fabricated using an epitaxial substrate, the cost is high.
Meanwhile, with regard to an NPT type IGBT and FS type IGBT, there is known a method that uses a semiconductor substrate (hereafter referred to as an FZ substrate) formed by being cut out from a semiconductor ingot formed using a floating zone (FZ) method. Whichever semiconductor substrate of the epitaxial substrate and FZ substrate is used, these IGBTs are such that a low-dose, shallow p+ type collector layer is formed on the substrate back surface side. For example, a description will be given of the configurations of an NPT type IGBT and an FS type IGBT.
FIG. 12 is a sectional view showing the configuration of a heretofore known NPT type IGBT. As shown in FIG. 12, an n− type semiconductor substrate formed of an FZ substrate forms an n− type drift layer 101, and a p+ type base region 102 and n+ type emitter region 103 are selectively provided on one main surface (hereafter referred to as the front surface) side of the n− type drift layer 101. The n− type drift layer 101 has a function as an active layer. A gate electrode 105 is provided across a gate oxide film 104 on the front surface of the substrate. An emitter electrode 106 is in contact with the n+ type emitter region 103 and p+ type base region 102, and is isolated from the gate electrode 105 by an interlayer dielectric film 107. A p+ type collector layer 108 and a collector electrode 109 are provided on the other main surface (hereafter referred to as the back surface) of the n− type semiconductor substrate.
FIG. 13 is a sectional view showing the configuration of a heretofore known FS type IGBT. As shown in FIG. 13, the element structure on the front surface side of the FZ substrate is the same as the element structure of the NPT type IGBT shown in FIG. 12. The FS type IGBT differs from the NPT type IGBT in that an n-type buffer layer 110 is provided between the n− type drift layer 101 and p+ type collector layer 108 on the back surface side of the FZ substrate. By using an FZ substrate in the NPT type IGBT and FS type IGBT in this way, the total thickness of the substrate is considerably less than that in a PT type IGBT.
Specifically, in the case of the FS type IGBT, the total thickness of the substrate is 50 μm to 200 μm. More specifically, for example, in the case of a power semiconductor element in a 600V breakdown voltage class, the total thickness of the substrate is in the region of 80 μm. By using an FZ substrate, it is possible to control the hole injection ratio by adjusting the total thickness of the substrate, because of which it is possible to realize high speed switching without carrying out lifetime control. Also, as an FZ substrate is less expensive than an epitaxial substrate, cost decreases.
When mounting this kind of power semiconductor element (chip), each electrode of the power semiconductor element is connected to a circuit pattern on an insulating substrate, a plate-like conductor (hereafter referred to as an external terminal), or the like. For example, there is a heretofore known method whereby the collector electrode (back surface electrode) on the back surface side of the substrate is connected by solder joining to an external terminal, while the emitter electrode (front surface electrode) on the front surface side of the substrate is connected to an external terminal by wire bonding using aluminum wire. Also, a method whereby the front surface electrode is joined by solder joining to an external terminal has been proposed in order to increase the mounting density of a module package, improve current density, reduce wiring capacity in order to increase switching speed, improve the semiconductor element cooling efficiency, and the like.
By connecting the front surface electrode of the power semiconductor element and the external terminal by solder joining rather than wire bonding, it is possible to eliminate the space needed for wire routing when wire bonding, and thus possible to greatly reduce the capacity of the module package. Also, it is possible to greatly reduce the wiring capacity of a joint portion between the power semiconductor element and external terminal.
Furthermore, by solder joining the front surface electrode of the power semiconductor element and the external terminal, the current limitation caused by the wire resistance that occurs in wire bonding is eliminated, because of which it is possible to improve the current density. Also, as each of the front surface electrode and back surface electrode is connected to an external terminal (for example, a copper plate), it is also possible to cool the power semiconductor element directly with cooling water or the like, and it is thus possible to considerably improve the power semiconductor element cooling efficiency.
In order to solder join the front surface electrode of the power semiconductor element and the external terminal, it is necessary to provide a metal layer (for example, nickel) with good solder wettability on the surface of the front surface electrode. Forming a metal layer with good solder wettability on the surface of the front surface electrode using a plating process has been proposed as a method of solder joining the front surface electrode of the power semiconductor element and the external terminal (for example, refer to JP-A-2005-19798).
For example, an electroless plating method is known as a method of forming a metal layer using a plating process. However, when a dicing line (semiconductor substrate cutting reserve) is exposed on the front surface of the semiconductor substrate, a plating layer is also formed on the dicing line surface by the electroless plating process, and the front surface electrode potential and substrate potential become the same across the plating layer. Also, there is concern that a plating layer will also be formed on the outer peripheral portion, in which no element structure is to be formed, of the semiconductor substrate (wafer), and furthermore, that a plating layer will be formed as far as the back surface of the semiconductor substrate.
When a plating layer is formed as far as the outer peripheral portion or back surface of the semiconductor substrate, there is a problem in that variation occurs in a plating layer formed on the front surface side of the semiconductor substrate. A method whereby a dicing line on the front surface side of a substrate, or a substrate side surface, is covered with a dielectric film or resin has been proposed as a method of suppressing this kind of plating layer variation (for example, refer to JP-A-2006-156772 and Japanese Patent No. 3,831,846).
However, even when covering the dicing line with a dielectric film or resin, for example, zinc residue remaining due to insufficient cleaning after a zinc substitution process during double zincate treatment carried out as preprocessing when forming a nickel layer using an electroless plating process (hereafter referred to as an electroless nickel plating process), suspended solids in the plating solution, and the like, become a nucleus, and there is concern that a plating layer will be formed on the semiconductor substrate back surface side, which is not activated with respect to the plating solution.
It may happen that a plating layer (for example, a nickel layer) anomalously deposited on an originally unintended portion (for example, the back surface electrode of the semiconductor substrate) in this way becomes detached due to oscillation of the semiconductor substrate in the plating solution, and falls into the plating solution. Then, the fallen plating layer (nickel layer) becomes a nucleus, and continuous deposition of the metal (nickel) configuring the plating layer begins in the plating tank, because of which the concentration of the metal configuring the plating layer (the nickel concentration) in the plating solution decreases.
An electroless plating process is such that the plating processing time is determined from a deposition speed measured in advance. Because of this, when the composition of the plating solution changes, the electroless plating process is carried out at a deposition speed different from the deposition speed measured in advance, and the desired thickness of plating layer can no longer be obtained in the predetermined plating processing time. Consequently, a problem occurs in that the plating tank has to be cleaned and the plating solution changed.
In order to eliminate this kind of problem, a method whereby the semiconductor substrate is fixed and a plating process carried out using a dedicated jig with a structure such that the plating solution does not reach the back surface side of the substrate has been proposed as a method of forming a plating layer on only the front surface side of the semiconductor substrate. Also, a method whereby a protective film is formed by applying a resist to a portion on which no plating layer is to be formed, such as the back surface or side surface of the semiconductor substrate, and an electroless plating process subsequently carried out, has been proposed as another method.
Also, a method whereby an adhesive solution is applied to the surface on the side of the semiconductor substrate opposite to the surface to be processed and, after the fluidity of the adhesive solution is reduced by preliminary drying, thus enabling the maintaining of form as an adhesive layer, a support plate is attached, has been proposed as a method of carrying out a predetermined process in a condition wherein the surface of the semiconductor substrate is partially covered (for example, refer to JP-A-2005-191550).
Also, a method whereby a PET substrate is attached to the surface on a surface side element structure portion side of a semiconductor wafer, after which a back surface structure is fabricated on the back surface of the semiconductor wafer with the PET substrate still in the attached condition, has been proposed as another method (for example, refer to JP-A-2007-317964).
Also, a method whereby an adhesive layer is formed on the surface on the side of a semiconductor wafer opposite to the surface to be processed, after which a light permeable supporting body, such as glass on which a photothermal conversion layer including a light absorbing agent and a thermally degradable resin is formed in advance, is attached across the adhesive layer to the semiconductor wafer, has been proposed as another method (for example, refer to JP-A-2004-64040).
Also, a method whereby a process using a chemical is carried out on a main surface of the semiconductor substrate in a condition wherein the side surface of the semiconductor substrate is still covered with tape has been proposed as another method (for example, refer to JP-A-2011-219503, JP-A-2011-222541, and JP-A-2006-352078). Also, a method whereby tape is attached to one main surface of the semiconductor substrate, after which a plating process is carried on the other main surface of the semiconductor substrate, has been proposed as another method (for example, refer to JP-A-2011-222898).